The present invention relates generally to the manufacture and analysis of semiconductor devices and, more particularly, to the reconfiguration of such devices after their initial construction.
In recent years, the semiconductor industry has realized tremendous advances in technology which have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of MIPS (millions of instructions per second) to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
To increase the number of pad sites available for a die, different chip packaging techniques have been used. One of many related package types is called xe2x80x9ccontrolled-collapse chip connectionxe2x80x9d or xe2x80x9cflip chipxe2x80x9d packaging, and uses bonding pads and metal (solder) bumps. The bonding pads need not be on the periphery of the die and hence are moved to the site nearest the transistors and other circuit devices formed in the die. As a result, the electrical path to the pad is shorter. Electrical connection to the package is made when the die is flipped over the package with corresponding bonding pads. Each bump connects to a corresponding package inner lead. The resulting packages have a lower profile and have lower electrical resistance and a shortened electrical path. The output terminals of the package may be ball-shaped conductive-bump contacts (usually solder, or other similar conductive material) are typically disposed in a rectangular array. These packages are occasionally referred to as xe2x80x9cBall Grid Arrayxe2x80x9d (BGA) packages. Alternatively, the output terminals of the package may be pins; such a package is commonly known as a Pin Grid Array (PGA) package.
For BGA, PGA and other types of packages, once the die is attached to the package, the backside portion of the die remains exposed. The transistors and other circuitry are generally formed in a very thin epitaxially grown silicon layer on a single crystal silicon wafer from which the die is singulated. The side of the die including the epitaxial layer containing the transistors, and the other active circuitry, is often referred to as the circuit side of the die or front side of the die. The circuit side of the die is positioned very near the package and opposes the backside of the die. Between the backside and the circuit side of the die is single crystalline silicon. The positioning of the circuit side provides many of the advantages of the flip chip.
In some instances, the orientation of the die with the circuit side face down on a substrate may be a disadvantage or present new challenges. For example, when a circuit fails or when it is necessary to modify a particular chip, access to the transistors and circuitry near the circuit side is typically obtained only from the backside of the chip. This is challenging since the transistors are in a very thin layer (about 10 micrometers) of silicon buried under the bulk silicon (greater than 500 micrometers). Thus, the circuit side of the flip chip die is not visible or accessible for viewing using optical or scanning electron microscopy.
Techniques have been developed to access the circuit even though the integrated circuit (IC) is buried under the bulk silicon. For example, near-infrared (nIR) microscopy is capable of imaging the circuit because silicon is relatively transparent in these wavelengths of the radiation. However, because of the absorption losses of nIR radiation in silicon, it is generally required to thin the die to less than 100 microns in order to view the circuit using nIR microscopy. For a die that is 725 microns thick, at least 625 microns of silicon is removed before nIR microscopy can be used.
Thinning the die for failure analysis of a flip chip bonded IC is usually accomplished by first globally thinning, wherein the silicon is thinned across the entire die surface. The silicon is globally thinned to allow viewing of the active circuit from the back side of the die using nIR microscopy. Mechanical polishing is one method for global thinning. Using nIR microscopy, an area is identified for accessing to a particular area of the circuit. Local thinning techniques such as laser microchemical etching are used to thin the silicon an area to a level that is thinner than the die size. One method for laser microchemical etching of silicon is accomplished by focusing a laser beam on the backside of the silicon surface to cause local melting of silicon in the presence of chlorine gas. The molten silicon reacts very rapidly with chlorine and forms silicon tetrachloride gas, which leaves the molten (reaction) zone. A specific example silicon-removal process uses the 9850 SiliconEtcher(trademark) tool by Revise, Inc. (Burlington, Mass). This laser process is suitable for both local and global thinning by scanning the laser over a part of, or the whole, die surface.
During failure analysis, or for design debug, it is sometimes desirable to make electrical contact and probe certain circuit nodes on the circuit side or front side of the die, or to reconfigure the conductors in an integrated circuit. For a flip chip die, this would generally involve milling through the backside of the die to access the node, or milling to the node and subsequently depositing a metal on the node. Accurately determining the thickness of the silicon in the backside, however, is not readily determined; and when not controlled properly, can result in destruction of the circuitry that is to be analyzed or debugged.
Unlike a flip-chip die, the upper-level interconnects are immediately accessible via the backside of a normally-oriented die, and several techniques have been developed or explored for use in restructuring such a die. For example, for laser-linking of conductors, special sites have been fabricated consisting of sandwiches of Al, SiO2, amorphous Si, SiO2, and Al, and these sites can be reliably laser-fused to produce a desired short circuit. Laser microchemical etching and deposition have been reported for such reconstruction. For removal of Al, a liquid etchant covers the surface and etching occurs under the laser spot. For the addition of poly-silicon conductors, the circuit is placed in an ambient of 200 Torr of diborane-doped silane gas. The e-beam charging of gates has also been demonstrated as a technique for restructuring integrated circuits or programming EPROM""s (erasable programmable read-only memory). For a normally-oriented die, these techniques are burdensome in that each involves undesirable fabrication steps, wet chemistry, unduly large access areas, or relatively high resistance links.
There are additional drawbacks when considering use of the reported techniques for rebuilding a node via backside access in a flip-chip die. For example, accessing an interconnect via the backside of a flip-chip involves not only the above-described access and rebuilding problems but also reaching the interconnect. Because the interconnects are located on the opposite side of the active regions and isolation (e.g. trench isolation) regions that are used to separate the active regions, reaching the interconnects via local thinning results in boring through and destroying these regions.
The method and apparatus described herein involves a tool adapted to mill through the bulk silicon in the backside of a semiconductor device and to reconstruct circuitry after boring through circuit regions blocking the circuitry to be modified. One embodiment involves determining where the particular areas of the epitaxial regions lie, boring through these epitaxial regions, reconfiguring a target node and then repairing these bored regions by depositing materials such as silicon and trench isolation and implanting dopants in the reverse order as which they were milled.
In a more particular embodiment, a system includes a focused-ion beam (FIB) device having a silicon depositor, a focused-implanter, an oxidizer, and includes a focused localized heating source for annealing and (optionally) a metal deposition device.
In another embodiment, a system includes a focused-ion beam (FIB) device having a silicon depositer, a focused-implanter, an oxidizer, a laser tool for annealing, and (optionally) a metal deposition device.
In yet another embodiment, an apparatus is used for reconstructing a flip-chip semiconductor device having a backside and an opposite circuit side that includes a first region. The apparatus includes: an etching tool for removing substrate from the backside of the semiconductor devices and forming a via into the circuit side and beyond the first region; end point detection for determining a depth indicating the location of the first region; a focused ion-beam generator adapted to reconstruct a second region in the circuit side using the via for access; and a tool that rebuilds the first region using the via for access.
The above summary is not intended to describe each illustrated embodiment or every implementation of the present invention. Other particular embodiments of the invention provide for related methods and more specific implementations. The figures and the detailed description which follow more particularly exemplify these embodiments.